| [NOCS'21] |
A. Monemi, I. Perez, N. Leyva, E. Vallejo, R. Beivide, and M. Moretó: PlugSMART: a pluggable open-source module to implement multihop bypass in Networks-on-Chip. International Symposium on Networks?on?Chip (NOCS), Oct 2021. Nominated to the Best Paper Award. |
| [FPL'21a] |
A. Haghi, S. Marco-Sola, Ll. Alvarez, D. Diamantopoulos, C. Hagleitner, and M. Moretó: An FPGA Accelerator of the Wavefront Algorithm for Genomics Pairwise Alignment. International Conference on Field-Programmable Logic and Applications (FPL), Sept 2021. Nominated to the Best Paper Award. |
| [FPL'21b] |
V. Kostalabros, J. Ribes-Gonzalez, O. Farras, M. Moretó, and C. Hernandez. HLS-Based HW/SW Co-Design of the Post-Quantum Classic McEliece Cryptosystem. International Conference on Field-Programmable Logic and Applications (FPL), Sept 2021. |
| [FPL'21c] |
D. Castells-Rufas, S. Marco-Sola, Q. Aguado-Puig, A. Espinosa-Morales, J. C. Moure, Ll. Alvarez, and M. Moretó. OpenCL-based FPGA Accelerator for Semi-Global Approximate String Matching Using Diagonal Bit-Vectors. XXXX. International Conference on Field-Programmable Logic and Applications (FPL), Sept 2021. |
| [EuroPar'21] |
V. Dimic, M. Moretó, M. Casas, and M. Valero: PrioRAT: Criticality-Driven Prioritization Inside the On-Chip Memory Hierarchy. Euro-Par 2021, Aug 2021. |
| [ICPP'21] |
G. Lopez-Paradis, A. Armejach, and M. Moretó: gem5+RTL: l: A Framework to Enable RTL Models Inside a Full-System Simulator. International Conference on Parallel Processing (ICPP), Aug 2021. |
| [ICS'21] |
A. Barredo, A. Armejach, J. Beard, and M. Moretó: PLANAR: A Programmable Accelerator for Near-Memory Data Rearrangement. International Conference on Supercomputing (ICS), June 2021. |
| [ETS'21] |
G. Cabo, F. Bas, R. Lorenzo, D. Trilla, S. Alcaide, M. Moretó, C. Hernandez, and J. Abella: SafeSU: an Extended Statistics Unit for Multicore Timing Interference. European Test Symposium (ETS), May 2021. |
| [HPCA'21] |
J. Pavon, I. Vargas-Valdivieso, A. Barredo, J. Marimon, M. Moretó, F. Moll, O.S. Unsal, M. Valero, and A. Cristal: VIA: A Smart Scratchpad for Vector Units with Application to Sparse Matrix Computations. International Symposium on High-Performance Computer Architecture (HPCA), pp. 921-934, Feb 2021. |
| [DATE'21] |
A. Armejach, B. Brank, J. Cortina, F. Dolique, T. Hayes, N. Ho, P.A. Lagadec, R. Lemaire, G. Lopez-Paradis, L. Marliac, P. Marcuello, M. Moretó, D. Pleiter, X. Tan and S. Derradji: Mont-Blanc 2020: Towards Scalable and Power Efficient European HPC Processors. Design, Automation and Test in Europe Conference and Exhibition (DATE), Feb 2021. |
| [ICPR'20] |
M. Cancilla, L. Canalini, F. Bolelli, S. Allegretti, S. Carrion, R. Paredes, J.A. Gomez, S. Leo, M.E. Piras, L. Pireddu, A. Badouh, S. Marco-Sola, Ll. Alvarez, M. Moretó, and C. Grana: The DeepHealth Toolkit: A Unified Framework to Boost Biomedical Applications. International Conference on Pattern Recognition (ICPR), pp. 9881-9888, Jan 2021. |
| [SC'20] |
L. Jaulmes, M. Moretó, M. Valero, M. Erez, and M. Casas: Runtime-guided ECC protection using online estimation of memory vulnerability. International Conference for High Performance Computing, Networking, Storage and Analysis (SC), Nov 2020. |
| [DCIS'20] |
J. Abella, C. Bulla, G. Cabo, F.J. Cazorla, A. Cristal, M. Doblas, R. Figueras, A. Gonzalez, C. Hernandez, C. Hernandez, V. Jimenez, L. Kosmidis, V. Kostalabros, R. Langarita, N. Leyva, G. Lopez-Paradis, J. Marimon, R. Martinez, J. Mendoza, F. Moll, M. Moretó, J. Pavon, C. Ramirez, M.A. Ramirez, C. Rojas-Morales, A. Rubio, A. Ruiz, N. Sonmez, V. Soria, Ll. Teres, O.S. Unsal, M. Valero, I. Vargas-Valdivieso, L. Villa: An Academic RISC-V Silicon Implementation Based on Open-Source Components. XXXV Conference on Design of Circuits and Integrated Systems (DCIS). Nov 2020. |
| [FPL'20] |
A. Haghi, Ll. Alvarez, J. Polo, D. Diamantopoulos, C. Hagleitner, and M. Moretó: A Hardware/Software Co-Design of K-mer Counting Using a CAPI-Enabled FPGA. International Conference on Field-Programmable Logic and Applications (FPL), pp. 57-64, Sept 2020. |
| [ISPASS'20] |
I. Perez, E. Vallejo, M. Moretó, and R. Beivide: BST: A BookSim-Based Toolset to Simulate NoCs with Single- and Multi-Hop Bypass. International Symposium on Performance Analysis of Systems and Software (ISPASS), pp. 47-57, Aug 2020. |
| [ICS'20] |
V. Dimic, M. Moretó, M. Casas, J. Ciesko, and M. Valero: RICH: implementing reductions in the cache hierarchy. International Conference on Supercomputing (ICS), pp. 16:1-16:13, July 2020. |
| [ICS'20] |
I. Sanchez-Barrera, D. Black-Schaffer, M. Casas, M. Moretó, A. Stupnikova, M. Popov: Modeling and optimizing NUMA effects and prefetching with machine learning. International Conference on Supercomputing (ICS), pp. 34:1-34:13, July 2020. |
| [HPCA'20] |
A. Barredo, J.M. Cebrian, M. Moretó, M. Casas, and M. Valero: Improving Predication Efficiency through Compaction/Restoration of SIMD Instructions. International Symposium on High-Performance Computer Architecture (HPCA), pp. 717-728, Feb 2020. |
| [IOLTS'19] |
L. Jaulmes, M. Moretó, M. Valero, and M. Casas: A Vulnerability Factor for ECC-protected Memory. International Symposium on On-Line Testing and Robust System Design (IOLTS), pp. 176-181, July 2019. |
| [ICS'19] |
D. Chasapis, M. Moretó, M. Schulz, B. Rountree, M. Valero and M. Casas: Power efficient job scheduling by predicting the impact of processor manufacturing variability. International Conference on Supercomputing (ICS), pp. 296-307, Phoenix, USA, June 2019. |
| [ICS'19] |
E. Castillo, N. Jain, M. Casas, M. Moretó, M. Schulz, R. Beivide, M. Valero and A. Bhatele: Optimizing computation-communication overlap in asynchronous task-based programs. International Conference on Supercomputing (ICS), pp. 380-391, Phoenix, USA, June 2019. |
| [IPDPS'19] |
C. Gomez, F. Martinez, A. Armejach, M. Moret, F. Mantovani and M. Casas: Design Space Exploration of Next-Generation HPC Machines. International Parallel & Distributed Processing Symposium (IPDPS), pp. 54-65. Apr 2019. |
| [ISUM'19] |
N.I. Leyva-Santes, I. Perez, C. Hernandez-Calderon, E. Vallejo, M. Moretó, R. Beivide, M.A. Ramirez-Salinas, L.A. Villa-Vargas: Lagarto I RISC-V Multi-core: Research Challenges to Build and Integrate a Network-on-Chip. International Conference on Supercomputing in Mexico (ISUM), pp. 237-248, Monterrey, Mexico, Mar 2019. |
| [SC'18] |
P. Caheny, Ll. Alvarez, M. Valero, M. Moretó, and M. Casas. Runtime-Assisted Cache Coherence Deactivation in Task Parallel Programs. International Conference for High Performance Computing, Networking, Storage and Analysis (SC), Dallas, USA, Nov 2018. |
| [PACT'18] |
A. Armejach, H. Caminal, J. M. Cebrian, R. Gonzalez-Arbequilla, C. Adeniyi-Jones, M. Valero, M. Casas, and M. Moretó. Stencil Codes on a Vector Length Agnostic Architecture. International Conference on Parallel Architectures and Compilation Techniques (PACT), Limassol, Cyprus, Nov 2018. |
| [ICS'18] |
I. Sanchez-Barrera, M. Moretó, E. Ayguade, J. Labarta, M. Valero, and M. Casas. Reducing Data Movement on Large Shared Memory Systems by Exploiting Computation Dependencies. International Conference on Supercomputing (ICS), Beijing, China, June 2018. |
| [ICS'18] |
Ll. Alvarez, M. Casas, J. Labarta, E. Ayguade, M. Valero, and M. Moretó. Runtime-Guided Management of Stacked DRAM Memories in Task Parallel Programs. International Conference on Supercomputing (ICS), Beijing, China, June 2018. |
| [ISC'18] |
K. Chronaki, M. Casas. M. Moretó, J. Bosch, and R. M. Badia. TaskGenX: A Hardware-Software Proposal for Accelerating Task Parallelism. International Conference on High Performance Computing (ISC), Frankfurt, Germany, June 2018. |
| [HPCA'18] |
E. Castillo, Ll. Alvarez, M. Moretó, M. Casas, E. Vallejo, J.L. Bosque, R. Beivide and M. Valero: Architectural Support for Task Dependence Management with Flexible Software Scheduling. International Symposium on High-Performance Computer Architecture (HPCA), Vienna, Austria, February 2018. |
| [SBAC-PAD'17] |
Q. Liu, M. Moretó, J. Abella, F. J. Cazorla, M. Valero: SEDEA: A Sensible Approach to Account DRAM Energy in Multicore Systems. International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD), Campinas, Brazil, October 2017. |
| [MASCOTS'17] |
D. Roca, D. Nemirovsky, M. Casas, M. Moretó, M. Valero, M. Nemirovsky: iQ: An Efficient and Flexible Queue-Based Simulation Framework. IEEE International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems (MASCOTS), Alberta, Canada, September 2017. |
| [EuroPAR'17] |
V. Dimic, M. Moretó, M. Casas, and M. Valero: Runtime-Assisted Shared Cache Insertion Policies Based on Re-Reference Intervals. Euro-Par, Santiago de Compostela, Spain, August 2017. |
| [ICS'17] |
C. Ortega, M. Moretó, M. Casas, R. Bertran, A. Buyuktosunoglu, A. Eichenberger and P. Bose. libPRISM: An Intelligent Adaption of Prefetch and SMT Levels. International Conference on Supercomputing (ICS), Chicago, USA, June 2017. |
| [IPDPS'17] |
I. Brumar, M. Casas, M. Moretó, G. Sohi and M. Valero. ATM: Approximate Task Memoization in the Runtime System. International Parallel & Distributed Processing Symposium (IPDPS), Orlando, USA, May 2017. |
| [SC'16] |
T. Grass, C. Allande, A. Armejach, A. Rico, E. Ayguade, J. Labarta, M. Valero, M. Casas, and M. Moretó. MUSA: A multi-level simulation approach for next-generation HPC machines. International Conference for High Performance Computing, Networking, Storage and Analysis (SC), Salt Lake City, USA, November 2016. |
| [PACT'16] |
P. Caheny, M. Casas, M. Moretó, H. Gloaguen, M. Saintes, E. Ayguade, J. Labarta, and M. Valero. Reducing cache coherence traffic with hierarchical directory cache and NUMA-aware runtime scheduling. International Conference on Parallel Architectures and Compilation Techniques (PACT), Haifa, Israel, September 2016. [PDF] |
| [ICS'16] |
D. Chasapis, M. Casas, M. Moretó, M. Schulz, E. Ayguade, J. Labarta, and M. Valero. Runtime-Guided Mitigation of Manufacturing Variability in Power-Constrained Multi-Socket NUMA Nodes. International Conference on Supercomputing (ICS), Istanbul, Turkey, June 2016. [PDF] |
| [IPDPS'16] |
E. Castillo, M. Moretó, M. Casas, Ll. Alvarez, E. Vallejo, K. Chronaki, R. M. Badia, J. L. Bosque, R. Beivide, E. Ayguade, J. Labarta, and M. Valero. CATA: Criticality Aware Task Acceleration for Multicore Processors. International Parallel & Distributed Processing Symposium (IPDPS), Chicago, USA, May 2016. |
| [ISPASS'16] |
T. Grass, A. Rico, M. Casas, M. Moretó and E. Ayguade. TaskPoint: Sampled Simulation of Task-Based Programs. International Symposium on Performance Analysis of Systems and Software (ISPASS), Uppsala, Norway, April 2016. |
| [SC'15] |
L. Jaulmes, M. Casas, M. Moretó, E. Ayguade, J. Labarta, and M. Valero. Exploiting Asynchrony from Exact Forward Recovery for DUE in Iterative Solvers. International Conference for High Performance Computing, Networking, Storage and Analysis (SC), Austin, USA, November 2015. Nominated to the Best Paper Award. [PDF] |
| [PACT'15] |
Ll. Alvarez, M. Moretó, M. Casas, E. Castillo, X. Martorell, J. Labarta, E. Ayguade, and M. Valero. Runtime-Guided Management of Hybrid Memory Hierarchies in Multicore Architectures. International Conference on Parallel Architectures and Compilation Techniques (PACT), San Francisco, USA, October 2015. |
| [EuroPAR'15] |
M. Casas, M. Moretó, Ll. Alvarez, E. Castillo, D. Chasapis, T. Hayes, L. Jaulmes, O. Palomar, O. S. Unsal, A. Cristal, E. Ayguade, J. Labarta, and M. Valero: Runtime-Aware Architectures. Euro-Par 2015, Vienna, Austria, pages 16-27. |
| [ISCA'15] |
Ll. Alvarez, Ll. Vilanova, M. Moretó, M. Casas, M. Gonzalez, X. Martorell, N. Navarro, E. Ayguade, and M. Valero. Coherence protocol for transparent management of scratchpad memories in shared memory manycore architectures. International Symposium on Computer Architecture, Portland, USA, June 2015. [PDF] |
| [EuroPAR'14] |
Q. Liu, M. Moretó, J. Abella, F. J. Cazorla, M. Valero: DReAM: Per-Task DRAM Energy Metering in Multicore Systems. Euro-Par 2014, Porto, Portugal, pages 111-123, August 2014. |
| [ISCA'13] |
H. Cook, M. Moretó, S. Bird, K. Dao, D. A. Patterson, and K. Asanović. A Hardware Evaluation of Cache Partitioning to Improve Utilization and Energy-Efficiency while Preserving Responsiveness. International Symposium on Computer Architecture, Tel Aviv, Israel, June 2013. [PDF] [Slides] |
| [DAC'13] |
J. A. Colmenares, G. Eads, S. Hofmeyr, S. Bird, M. Moretó, D. Chou, B. Gluzman, E. Roman, D. B. Bartolini, N. Mor, K. Asanović, and J. D. Kubiatowicz. Tessellation: Refactoring the OS around Explicit Resource Containers with Continuous Adaptation. Design Automation Conference. Austin, Texas, USA, June 2013. [PDF] |
| [DAC'13] |
S. Girbal, M. Moretó, A. Grasset, J. Abella, E. Quinones, F. J. Cazorla, S. Yehia. On the convergence of high-performance and mission critical markets. Design Automation Conference. Austin, Texas, USA, June 2013. [PDF] |
| [HPC'13] |
C. Camarero, E. Vallejo, C. Martínez, M. Moretó and R. Beivide. Task Mapping in Rectangular Twisted Tori. The 21st High Performance Computing Symposium (HPC). San Diego, CA, USA, April 2013. [PDF] |
| [MICRO'12] |
P. Radojković, P. M. Carpenter, M. Moretó, A. Ramirez, and F. J. Cazorla. Kernel Partitioning of Streaming Applications: A Statistical Approach to an NP-complete Problem. International Symposium on Microarchitecture (MICRO). Vancouver, Canada, December 2012. |
| [IISWC'12] |
S. Manousopoulos, M. Moretó, R. Gioiosa, N. Koziris, and F. J. Cazorla. Characterizing Thread Placement in the IBM POWER7 Processor. International Symposium on Workload Characterization (IISWC). San Diego, USA, November 2012. [PDF] |
| [ASPLOS'12] |
P. Radojković, V. Cakarević, M. Moretó, J. Verdu, A. Pajuelo, F. J. Cazorla, M. Nemirovsky, and M. Valero. Optimal Task Assignment in Multithreaded Processors: A Statistical Approach. Architectural Support for Programming Languages and Operating Systems (ASPLOS). London, UK, March 2012. [PDF] |
| [CF'10] |
M. Moretó, F. J. Cazorla, R. Sakellariou and M. Valero. Load Balancing Using Dynamic Cache Allocation. ACM International Conference on Computing Frontiers (CF). Bertinoro, Italy, May 2010. [PDF] |
| [IPDPS'10] |
K. Kedzierski, M. Moretó, F. J. Cazorla and M. Valero. Adapting Cache Partitioning Algorithms to Real pseudo-LRU Replacement Policies. IEEE International Parallel and Distributed Processing Symposium (IPDPS). Atlanta, USA, April 2010. [PDF] [Slides] |
| [PACT'09] |
C. Luque, M. Moretó, F. J. Cazorla, R. Gioiosa, A. Buyuktosunoglu and M. Valero.
ITCA: Inter-Task Conflict-Aware CPU Accounting for CMPs. International Conference on Parallel
Architectures and Compilation Techniques (PACT). Raleigh, North Carolina. September 2009. [PDF] |
| [CEC'08] |
P. A. Castillo, J. J. Merelo, M. Moretó, F. J. Cazorla, M. Valero, A. M. Mora, J. L. J. Laredo, and S.A. McKee. Evolutionary system for prediction and optimization of hardware architecture performance. IEEE Congress on Evolutionary Computation (CEC). Hong Kong. June 2008. |
| [HiPEAC'08] |
M. Moretó, F. J. Cazorla, A. Ramirez and M. Valero. MLP-aware dynamic cache partitioning. International Conference on High Performance Embedded Architectures and Compilers (Hipeac). Goteborg, Sweden, January 2008. |
| [SAMOS'07] |
M. Moretó, F. J. Cazorla, A. Ramirez and M. Valero. Online Prediction of Applications Cache Utility. International Symposium on Systems, Architectures, MOdeling and Simulation (SAMOS). July 2007. |
| [IPDPS'07] |
J. Cámara, M. Moretó, E. Vallejo, R. Beivide, C. Martínez, J. Miguel-Alonso and J. Navaridas. “Mixed-radix Twisted Torus Interconnection Networks”. IEEE International Parallel and Distributed Processing Symposium (IPDPS). Long beach, USA, March 2007. |
| [ISIT'06] |
C. Martínez, M. Moretó, R. Beivide and E. Gabidulin. “A Generalization of Perfect Lee Codes over Gaussian Integers”. IEEE International Symposium on Information Theory. Seattle, USA. July 2006. |
| [TC'21] |
C. Ortega, Ll. Alvarez, M. Casas, R. Bertran, A. Buyuktosunoglu, A.E. Eichenberger, P. Bose and M. Moretó: Intelligent Adaptation of Hardware Knobs for Improving Performance and Power Consumption. IEEE Trans. Computers 70(1), pp. 1-16, 2021. |
| [JoS'21] |
V. Soria-Pardos, A. Armejach, D. Suarez-Gracia, M. Moretó: On the use of many-core Marvell ThunderX2 processor for HPC workloads. J. Supercomput. 77(4), pp. 3315-3338, 2021. |
| [BIOINF'20] |
S. Marco-Sola, J. Carlos Moure, M. Moretó and A. Espinosa: Fast gap-affine pairwise alignment using the wavefront algorithm. Bioinformatics, 2020. |
| [TCBB'20] |
R. Langarita, A. Armejach, J. Setoain, P. Ibañez-Marin, J. Alastruey-Benede, and M. Moreto: Compressed Sparse FM-Index: Fast Sequence Alignment Using Large K-Steps. IEEE/ACM Transactions on Computational Biology and Bioinformatics (TCBB), 2020. |
| [FGCS'20] |
J.M. Cebrian, A. Barredo, H. Caminal, M. Moretó, M. Casas and M. Valero: Semi-automatic validation of cycle-accurate simulation infrastructures: The case for gem5-x86. Future Gener. Comput. Syst. 112, pp. 832-847, 2020. |
| [JoS'20] |
A. Armejach, H. Caminal, J.M. Cebrian, R. Langarita, R. Gonzalez-Alberquilla, C. Adeniyi-Jones, M. Valero, M. Casas and M. Moretó: Using Arm's scalable vector extension on stencil codes. J. Supercomput. 76(3), pp. 2039-2062, 2020. |
| [JoS'20] |
A. Barredo, J.M. Cebrian, M. Valero, M. Casas and M. Moretó: Efficiency analysis of modern vector architectures: vector ALU sizes, core counts and clock frequencies. J. Supercomput. 76(3), pp. 1960-1979, 2020. |
| [CCF'19] |
F. Gagliardi, M. Moretó, M. Olivieri and M. Valero: The international race towards Exascale in Europe. CCF Trans. High Perform. Comput. 1(1), pp. 3-13, 2019. |
| [JoS'19] |
A. Armejach, M. Casas, M. Moretó: Design trade-offs for emerging HPC processors based on mobile market technology. J. Supercomput. 75(9), pp. 5717-5740, 2019. |
| [JPDC'19] |
K. Chronaki, M. Moretó, M. Casas, A. Rico, R.M. Badia, E. Ayguadé and M. Valero: On the maturity of parallel applications for asymmetric multi-core processors. J. Parallel Distributed Comput. 127, pp. 105-115, 2019. |
| [TC'19] |
T. Grass, T.E. Carlson, A. Rico, G. Ceballos, E. Ayguade, M. Casas, and M. Moretó: Sampled Simulation of Task-Based Programs . IEEE Trans. Comput., vol. 68, issue 2, pp. 255-269, 2019. |
| [TPDS'18] |
L. Jaulmes, M. Moretó, E. Ayguade, J. Labarta, M. Valero, M. Casas. Asynchronous and Exact Forward Recovery for Detected Errors in Iterative Solvers. IEEE Trans. Parallel Distrib. Syst., vol. 29, issue 9, pp. 1961-1974, 2018. |
| [TPDS'18] |
P. Caheny, Ll. Alvarez, S. Derradji, M. Valero, M. Moretó and M. Casas: Reducing Cache Coherence Traffic with a NUMA-Aware Runtime Approach. IEEE Trans. Parallel Distrib. Syst., vol. 29, issue 5, pp. 1174-1187, 2018. |
| [JoS'18] |
H. Caminal, D. Caballero, J. M. Cebrian, R. Ferrer, M. Casas, M. Moretó, X. Martorell and M. Valero: Performance and energy effects on task-based parallelized applications. User-directed versus manual vectorization. The Journal of Supercomputing. To appear in 2018. |
| [TPDS'17] |
K. Chronaki, A. Rico, M. Casas, M. Moretó, R. M. Badia, E. Ayguade, J. Labarta, and M. Valero. Task Scheduling Techniques for Asymmetric Multi-Core Systems. IEEE Trans. Parallel Distrib. Syst., vol. 28, issue 7, July 2017. |
| [TODAES'16] |
Q. Liu, M. Moretó, J. Abella, F. J. Cazorla, and M. Valero. DReAM: An Approach to Estimate per-Task DRAM Energy in Multicore Systems. ACM Transactions on Design Automation of Electronic Systems (TODAES), vol. 22, issue 1, November 2016. [PDF] |
| [TC'16] |
P. Radojkovic, P. M. Carpenter, M. Moretó, V. Cakarevic, J. Verdu, A. Pajuelo, F. J. Cazorla, M. Nemirovsky, and M. Valero. Thread assignment in multicore/multithreaded processors: A statistical approach. IEEE Trans. Comput., vol. 65, issue 1, pages 256-269, 2016. |
| [TACO'16] |
D. Chasapis, M. Casas, M. Moretó, R. Vidal, E. Ayguade, J. Labarta and M. Valero. PARSECSs: Evaluating the Impact of Task Parallelism in the PARSEC Benchmark Suite. ACM Transactions on Architecture and Code Optimization (TACO). Presented at International Conference on High Performance and Embedded Architectures and Compilers (HiPEAC), Prague, Czech Republic, January 2016. [PDF] |
| [TACO'16] |
Q. Liu, M. Moretó, J. Abella, F. J. Cazorla, D. A. Jimenez, and M. Valero. Sensible Energy Accounting with Abstract Metering for Multicore Systems. ACM Transactions on Architecture and Code Optimization (TACO). Presented at International Conference on High Performance and Embedded Architectures and Compilers (HiPEAC), Prague, Czech Republic, January 2016. [PDF] |
| [CAL'14] |
Q. Liu, V. Jiménez, M. Moretó, J. Abella, F. J. Cazorla, and M. Valero. Per-task energy accounting in computing systems. IEEE Comput. Archit. Lett., vol. 13, issue 2, pages 85-88, 2014. |
| [SuperFRI'14] |
M. Valero, M. Moretó, M. Casas, E. Ayguade and J. Labarta. Runtime-Aware Architectures: A First Approach. International Journal on Supercomputing Frontiers and Innovations (SuperFRI), vol. 1, issue 1, pages 29-44, June 2014. [PDF] |
| [TACO'13] |
Q. Liu, M. Moretó, V. Jimenez, J. Abella, F. J. Cazorla, and M. Valero. Hardware Support for Accurate Per-Task Energy Metering in Multicore Systems. ACM Transactions on Architecture and Code Optimization (TACO), vol. 10, num. 4, Dec 2013. Presented at International Conference on High Performance and Embedded Architectures and Compilers (HiPEAC), Vienna, Austria, January 2014. |
| [TACO'13] |
C. Luque, M. Moretó, F. J. Cazorla, and M. Valero. Fair CPU Time Accounting in CMP+SMT Processors. ACM Transactions on Architecture and Code Optimization (TACO). Presented at International Conference on High Performance and Embedded Architectures and Compilers (HiPEAC), Berlin, Germany, January 2013. [Slides] |
| [ToC'12] |
C. Luque, M. Moretó, F. J. Cazorla, R. Gioiosa, A. Buyuktosunoglu and M. Valero. CPU Accounting for Multicore Processors. IEEE Transactions on Computers, vol. 61, issue 2, February 2012. [PDF] |
| [Micro'11] |
J. Gonzalez, J. Gimenez, M. Casas, M. Moretó, A. Ramirez, J. Labarta and M. Valero. Simulating Whole Supercomputer Applications. IEEE Micro. Vol. 31, no. 3, May/June 2011. [PDF] |
| [TPDS'10] |
J. Cámara, M. Moretó, E. Vallejo, R. Beivide, C. Martínez, J. Miguel-Alonso and J. Navaridas. Twisted Torus Topologies for Enhanced Interconnection Networks. IEEE Trans. Parallel Distrib. Syst., vol. 21, no. 12, December 2010. [PDF] |
| [CAL'09] |
C. Luque, M. Moretó, F. J. Cazorla, R. Gioiosa, A. Buyuktosunoglu, and M. Valero. CPU accounting in CMP Processors. IEEE Computer Architecture Letters, vol. 9, issue 1, April
2009. |
| [OSR'09] |
M. Moretó, F. J. Cazorla, A. Ramirez, R. Sakellariou and M. Valero. FlexDCP: a QoS framework for CMP architectures. ACM SIGOPS Operating System Review, Special Issue on the Interaction among the OS, Compilers, and Multicore Processors, April 2009. |
| [ToC'08] |
C. Martinez, M. Moretó, R. Beivide, E. Gabidulin and E. Stafford. Modeling Toroidal Networks with the Gaussian Integers. IEEE Transactions on Computers, vol. 57, no. 8, August 2008. |
| [Micro'08] |
K. J. Nesbit, M. Moretó, F. J. Cazorla, A. Ramirez, M. Valero, and
J. E. Smith. Multicore Resource Management. IEEE Micro, special issue on Interaction of Computer Architecture and Operating
System in the Manycore Era, vol. 38, no. 3, May/June 2008. |
| [ToHiPEAC'08] |
M. Moretó, F. J. Cazorla, A. Ramirez and M. Valero. Dynamic Cache Partitioning based on the MLP of Cache Misses. Transactions on High Performance Embedded Architectures and Compilers. vol. 3, no. 1, March 2008. |
| [CAL'07] |
M. Moretó, F. J. Cazorla, A. Ramirez and M. Valero. Explaining Dynamic Cache
Partitioning Speed Ups. IEEE Computer Architecture Letters, vol. 6, no. 1, March
2007. |
| [IJPP'06] |
C. Martínez, E. Vallejo, R. Beivide, C. Izu and M. Moretó. “Dense Gaussian Networks: Suitable Topologies for On-Chip Multiprocessors”. International Journal of Parallel Programming, Vol. 33, No. 3, June 2006. |
| [DATE'20] |
J. Abella, G. Cabo, F.J. Cazorla, A. Cristal, R. Figueras, A. Gonzalez, C. Hernandez, C. Hernandez, V. Kostalabros, N. Leyva, J. Marimon, R. Martinez, J. Mendoza, F. Moll, M. Moretó, J. Pavon, C. Ramirez, M. A. Ramirez, C. Rojas, A. Rubio, A. Ruiz, N. Sonmez, Ll. Teres, O. Unsal, M. Valero, I. Vargas, and L. Villa: Lagarto: First Silicon RISC-V Academic Processor Developed in Spain. DATE 2020 University Booth. |
| [RedRV'20] |
F. Moll, M. Moretó, M. A. Ramirez, Ll. Teres and M. Valero: Lagarto RISC-V on Silicon (1st Edition). Poster in the Red RISC-V 2020 meeting. |
| [IWOMP'19] |
A. Rico, I. Sanchez Barrera, J.A. Joao, J. Randall, M. Casas, and M. Moretó: On the Benefits of Tasking with OpenMP. IWOMP 2019: 217-230. |
| [MP'19] |
L. Jaulmes, M. Moretó, M. Valero and M. Casas: Memory Vulnerability: A Case for Delaying Error Reporting. MultiProg 2019. |
| [PACT'19] |
A. Barredo, J. C. Beard, and M. Moretó: SPiDRE: Accelerating Sparse Memory Access Patterns. PACT 2019. |
| [PACT'19] |
A. Barredo, J.M. Cebrian, M. Moretó, M. Casas, and M. Valero: An Optimized Predication Execution for SIMD Extensions. PACT 2019: 479-480. |
| [PPoPP'19] |
E. Castillo, N. Jain, M. Casas, M. Moretó, M. Schulz, R. Beivide, M. Valero, and A. Bhatele: Optimizing computation-communication overlap in asynchronous task-based programs. PPoPP 2019: 415-416. |
| [AACBB'18] |
C. Bulla, Ll. Alvarez and M. Moretó: Are Next-Generation HPC Systems Ready for Population-level Genomics Data Analytics? Workshop on Accelerator Architecture in
Computational Biology and Bioinformatics. Vienna, Austria. |
| [PPoPP'18] |
I. Sanchez Barrera, M. Casas, M. Moretó, E. Ayguadé, J. Labarta and M. Valero: Graph partitioning applied to DAG scheduling to reduce NUMA effects. PPoPP 2018, Vienna, Austria. |
| [EuroPAR'17] |
I. Pietri, S. Zhuang, M. Casas, M. Moretó and R. Sakellariou: Evaluating Scientific Workflow Execution on an Asymmetric Multicore Processor. Euro-Par Workshops 2017, Santiago de Compostela, Spain. |
| [PACT'16] |
K. Chronaki, M. Moretó, M. Casas, A. Rico, R. M. Badia, E. Ayguade, J. Labarta, and M. Valero. Exploiting Asymmetric Multi-Core Processors with Flexible System Software. International Conference on Parallel Architectures and Compilation Techniques (PACT), Haifa, Israel, September 2016. [PDF] |
| [IWOMP'15] |
R. Vidal, M. Casas, M. Moretó, D. Chasapis, R. Ferrer, X. Martorell, E. Ayguadé, J. Labarta, M. Valero. Evaluating the Impact of OpenMP 4.0 Extensions on Relevant Parallel Workloads. International Workshop on OpenMP (IWOMP), pages 60-72, Aachen, Germany. October 2015. |
| [ADAPT'15] |
D. Prat, C. Ortega, M. Casas, M. Moretó, and M. Valero, Adaptive and application dependent runtime guided hardware prefetcher reconfiguration on the IBM POWER7, ADAPT Workshop, 2015. [PDF] |
| [MuCoCos'14] |
T. Grass, A. Rico, M. Casas, M. Moretó and A. Ramirez. Evaluating Execution Time Predictability of Task-Based Programs on Multi-Core Processors. 7th International Workshop on Multi-/Many-Core Computing Systems (MuCoCos), August 2014. |
| [ModSim'13] |
M. Casas, M. Moretó, E. Ayguade, J. Labarta and M. Valero. MUSA: A Multiscale Simulation Approach for Exascale Computing. Workshop on Modeling & Simulation of Exascale Systems & Applications (ModSim), September 2013. |
| [HiRES'13] |
S. Girbal, M. Moretó, A. Grasset, J. Abella, E. Quinones, F. J. Cazorla, S. Yehia . The Next Convergence: High-performance and Mission-critical Markets. Workshop on High-performance and Real-time Embedded Systems (HiRES). January 21-23 2013, Berlin, Germany. |
| [BEARS'12] |
M. Moretó, Y. Lee, A. Waterman, H. Cook, S. Beamer, R. Avizienis, M. Popovic, R. Meade, G. Sandhu, R. Ram, V. Stojanovic, and K. Asanovic. Photonically Optimized Embedded Microprocessors (POEM). Berkeley EECS Annual Research Symposium (BEARS), February 23 2012, Berkeley, USA. |
| [ParLab'12] |
S. Bird, H. Cook, M. Moretó, K. Asanovic, and D. Patterson. Energy-Aware Last Level Cache Partitioning. Par Lab Winter Retreat, January 2012, Berkeley, USA. |
| [ACACES'11] |
Q. Liu, M. Moretó, J. Abella and F. J. Cazorla. Online Performance Prediction in Processors with DVFS Capabilities. ACACES 2011. Poster Abstracts. Advanced Computer Architecture and Compilation for Embedded Systems. L'Aquila, July 2011. |
| [ESTEC'10] |
M. Moretó, M. Paolieri, J. Abella, E. Quiñones, F. J. Cazorla and M. Valero. Hard Real-Time Capable Multicore Processors for Space Applications. ESTEC 1st Networking/Partnering Day. Poster Abstract. Noordwijk, Netherlands, January 2010. |
| [PACT'09] |
K. Kedzierski, M. Moretó, F. J. Cazorla and M. Valero. Pseudo-LRU based Cache Partitioning Algorithms. PACT 2009, Poster Abstracts. International Conference on Parallel
Architectures and Compilation Techniques (PACT). Raleigh, North Carolina. September 2009. |
| [EVOHot'08] |
P. A. Castillo, A. M. Mora, J. J. Merelo, J. L. J. Laredo, M. Moretó, F. J. Cazorla, M. Valero, and S.A. McKee. Architecture performance prediction using evolutionary artificial neural networks. European Workshop on Hardware Optimization Techniques (EVOHot). Napoli, Italy. March 2008. |
| [PACT'07] |
M. Moretó, F. J. Cazorla, A. Ramirez and M. Valero. MLP-aware dynamic cache partitioning. PACT 2007, Poster Abstracts. International Conference on Parallel
Architectures and Compilation Techniques (PACT). Brasov, September 2007. |
| [ACACES'06] |
M. Moretó, A. Ramírez and M. Valero. Reducing Simulation Time. ACACES 2006. Poster Abstracts. Advanced Computer Architecture and Compilation for Embedded Systems. L'Aquila, July 24-28, pp. 233-236. Academic Press, ISBN 90 382 0981 9. |
| [ACACES'05] |
M. Moretó, C. Martínez, R. Beivide, E. Vallejo and M. Valero. “Hierarchical Gaussian Topologies”. ACACES 2005, Poster Abstracts. Advanced Computer Architecture and Compilation for Embedded Systems. L'Aquila, July 25-29, pp. 211-214. Academic Press, ISBN 90 382 0802 2. |
