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The Barcelona Zettascale Laboratory (BZL) is a 3.5-year project (12/2022-06/2026) funded by the Spanish Ministry of Economic Affairs and Digital Transformation within the framework of the Recovery, Transformation and Resilience Plan, funded by the European Union – NextGenerationEU, grant agreement REGAGE22e00058408992. The project aims to design chips with technology based on open-source RISC-V hardware, to be used in future zettascale supercomputers. Participation as coordinator of the hardware efforts in the project. |
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Stratum (web) is a 5-year project (12/2023 - 11/2028) funded by the European Union's Horizon Europe Framework Programme, grant agreement 101137416. Stratum will develop a clinically demonstrated 3D Decision Support Tool for brain surgery guidance and diagnostics based on multimodal data processing through AI algorithms. Participation as PI at BSC in charge of coordinating the multi-disciplinary research team that is developing the heterogeneous HPC infraestructure in Stratum. |
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High Performance, Safe, Secure, Open-Source Leveraged RISC-V Domain-Specific Ecosystems (ISOLDE) is a 3-year project (2023-2026) funded by the European Union's Horizon Europe Framework Programme, grant agreement 101112274. ISOLDE will have high performance RISC-V processing systems and platforms, demonstrated for key European application domains such as automotive, space and IoT with the expectation that two years after completion ISOLDE’s high performance components will be used in industrial quality products. Leading BSC activities on Post-Quantum Cryptography (PQC) acceleration techniques. |
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Consolidated research group on Parallel Programming and Acceleration with Heterogeneous Architectures (PPHA) funded by the Catalan Agency for Management of Universities and Research Grants (AGAUR). This project is focused on high-performance heterogeneous computing architectures, including research on microarchitecture and the interaction of the architecture with the programming model, the operating systems and applications. Participation as team leader. |
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The European Processor Initiative (EPI) SGA2 is a 4-year project (2021-2025) funded by the European High Performance Computing Joint Undertaking (EuroHPC JU) under Framework Partnership Agreement No 800928 and Specific Grant Agreement No 101036168 (EPI SGA2). The aim of this project is to design and manufacture a first European general purpose processor and a European accelerator suitable for multiple markets (HPC, Big Data, automotive, Internet-of-Things, etc.). The goal of the project is to deploy a supercomputer based on EPI technology in selected European institutions by the end of the project. Leading a multi-group research effort at BSC to design an Arm-based general purpose processor for HPC. |
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High Performance Computing VIII (webpage) is a 4-year project funded by the Spanish Ministry of Science and Innovation under gran agreement no. PID2019-107255GB-C21. This project seeks to improve the efficiency of high-performance computing systems, including research on microarchitecture and multiprocessor architecture, compilers, operating systems, analysis, visualization and prediction tools, algorithms and applications. Participation as work package leader. |
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Arm-BSC Center of Excellence. In recognition of the leadership of BSC in pioneering Arm in HPC, and the success of the Mont-Blanc projects, the Arm-BSC Centre of Excellence (CoE) was established in 2019. Participation as the inaugural coordinator for this CoE.
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This collaboration between Lenovo and BSC pursues the acceleration of precision medicine applications on existing platforms with GPUs and FPGAs. Participation as principal investigator.
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Full member of the European Network on High Performance and Embedded Architecture and Compilation (HiPEAC). HiPEAC's mission is to steer and increase the European research in the area of high-performance and embedded computing systems, and stimulate cooperation between academia and industry, and between computer architects and tool builders. |
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eProcessor (European, extendable, energy-efficient, extreme-scale, extensible, Processor Ecosystem) is a 4-year project (2021-2025) funded by the European Union's H2020 Framework Programme, grant agreement 956702. The eProcessor project aims to build a new open out-of-order processor and accelerators and deliver a completely open European full-stack ecosystem. |
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High Performance Computer Architectures for Large-Scale Population Genome Data Analysis (GenArch) is a 2-year project (2022-2024) funded by the Spanish Ministry of Economy and Competitiveness, grant agreement TED2021-132634A-I00. GenArch will provide an end-to-end solution for genome data analysis applications that exploits heterogeneous compute systems with custom tightly-coupled accelerators. Participation as PI at BSC in charge of coordinating the multi-disciplinary research team that is developing the GenArch architecture and software stack. |
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Designing RISC-V-based Accelerators for next generation Computers (DRAC) is a 3-year project (2019-2023) funded by the ERDF Operational Program of Catalonia 2014-2020. DRAC will design, verify, implement and fabricate a high performance general purpose processor that will incorporate different accelerators based on the RISC-V technology, with specific applications in the field of security, genomics and autonomous navigation. Participation as coordinator of the project. |
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The European Processor Initiative (EPI) SGA1 is a 4-year project (2018-2022) funded by the European Union's Horizon 2020 research and innovation programme under grant agreement no. 826647. The aim of this project is to design and manufacture a first European general purpose processor and a European accelerator suitable for multiple markets (HPC, Big Data, automotive, Internet-of-Things, etc.). The goal of the project is to deploy a supercomputer based on EPI technology in selected European institutions by the end of the project. Leading a multi-group research effort at BSC to design an Arm-based general purpose processor for HPC.
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Deep-Learning and HPC to Boost Biomedical Applications for Health (DeepHealth) is a 3-year project (2019-2022) funded by the European Union's Horizon 2020 research and innovation programme under grant agreement no. 825111. The aim of DeepHealth is to offer a unified framework completely adapted to exploit underlying heterogeneous HPC and Big Data architectures; and assembled with state-of-the-art techniques in Deep Learning and Computer Vision. In particular, DeepHealth combines HPC infrastructures with deep learning techniques to support biomedical applications. Participation as work package leader at BSC. |
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FPGA acceleration-centric innovation on OpenPOWER (webpage). This collaboration between IBM and BSC pursues the development of FPGA-based acceleration of precision medicine workloads, as well as other workloads of the IBM-BSC Deep Learning Center, and the definition of future architectures to accelerate such workloads. Participation as principal investigator between 2018 and 2021. |
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Mont-Blanc 2020 (webpage) is a 3-year project funded by the European Union's H2020 Framework Programme (H2020/2014-2020) under grant agreements no. 779877. The aim of this project is to design a new type of computer architecture capable of setting future global HPC standards, built from energy efficient solutions used in embedded and mobile devices. Participation as group leader in charge of the emulation methodology of the envisioned design. |
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High Performance Computing VII (webpage) is a 4-year project funded by the Spanish Ministry of Science and Innovation under gran agreement no. TIN2015-65316-P. This project seeks to improve the efficiency of high-performance computing systems, including research on microarchitecture and multiprocessor architecture, compilers, operating systems, analysis, visualization and prediction tools, algorithms and applications. Participation as work package leader. |
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Riding on Moore's Law (RoMoL) is a 5-year project funded by an ERC Advanced Grant awarded to Prof. Mateo Valero under grant agreement no. 321253. RoMoL involves research in microarchitecture, runtime systems, compilers and programming languages, and has the objective to maximize positive synergies between current research activities in the Computer Sciences Department at BSC. Participation as a Senior Researcher between 2013 and 2018. Under the supervision of Prof. Valero, led the RoMoL research team together with Dr. Marc Casas. |
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Mont-Blanc 3 (webpage) is a 3-year project funded by the European Union's H2020 Framework Programme (H2020/2014-2020) under grant agreements no. 671697. The aim of this project is to design a new type of computer architecture capable of setting future global HPC standards, built from energy efficient solutions used in embedded and mobile devices. Participation as a Senior Researcher between 2015 and 2018. |
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Adaptive resource management for POWER architectures (webpage). This collaboration between IBM and BSC pursues the development of new adaptive algorithms to exploit prefetching enhancements in current and future POWER architectures and generalized concepts in cross-layer co-optimization for improving power-performance metrics in future POWER systems. Proposals on new harware requirements to support the development of a new generation of hardware-software co-managed adaptative systems will be pursued in this collaboration. Participation as a Senior Researcher between 2014 and 2017. |
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The Parallel Computing Laboratory (Par Lab) is a multidisciplinary research project exploring the future of parallel processing. With the end of sequential processor performance scaling, multicore processors provide the only path to increased performance and energy efficiency in all platforms from mobile to warehouse-scale computers. The Par Lab was created by a team of Berkeley researchers with the ambitious goal of enabling most programmers to be productive writing efficient, correct, portable software for hundreds of cores. |
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Tessellation (webpage) is a manycore OS targeted at the resource management challenges of emerging client devices. Tessellation is built on two central ideas: Space-Time Partitioning and Two-Level Scheduling. Tessellation was developed within Par Lab at the time of the postdoc at ICSI. |
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PROARTIS (webpage) is a 3-year project funded by the European Union's Seventh Framework Programme for research, technological development and demonstration under grant agreement no 249100. The aim of the PROARTIS project is to define new hardware and software architecture paradigms that, by design, exhibit a timing behaviour that can be effectively analysed with probabilistic techniques. Participation in the project as a postdoc between 2010 and 2011. |
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SARC (webpage) is a 4-year integrated project funded by the European Union's Sixth Framework Programme under grant agreement no. 027648. SARC project is concerned with long term research in advanced computer architecture. It focuses on a systematic scalable approach to systems design ranging from small energy critical embedded systems right up to large scale networked data servers. Participation in the project as a PhD student. |
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High Performance Computing IV, V and VI (webpage) are projects funded by the Spanish Ministry of Science and Innovation that aim to improve the efficiency of high-performance computing systems, including research on microarchitecture and multiprocessor architecture, compilers, operating systems, analysis, visualization and prediction tools, algorithms and applications. Participation first as a PhD student and then as a postdoc. |
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Consolidated research group on High Performance Computing Architectures (Arquitectura de Computadors d'Altes Prestacions, ACAP) funded by the Catalan Agency for Management of Universities and Research Grants (AGAUR). This project is focused on high-performance computing architectures, including research on microarchitecture and the interaction of the architecture with the programming model, the operating systems and applications. Participation first as a PhD student and then as a postdoc. |
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SoW on POWER5. In this project IBM and BSC intend to analyse, understand and evaluate the behaviour of SMT/CMP processor architectures, including but not limited to IBM's POWER5 processor. In particular, we analysed i) the interaction between the operating system and the IBM POWER5 processor; ii) the effect of the IBM POWER5 hardware prioritization on performance; iii) the SMT/CMP behaviour characteristics of HPC workloads; and iv) design space exploration of current and future SMT/CMP architectures. Participation as a PhD student. |
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MareIncognito (webpage). In 2007, research collaboration projects between IBM and BSC focused to enable BSC to the research on the design and development of new generation of Petascale Supercomputers. The code name for the project was MareIncognito. Participation as a PhD student. |
