Reliability at the circuit, microarchitecture, architecture and system level

Research activities

During my sabattical at Harvard University, I had the chance to work together with Professors David Brooks and Gu-Yeon Wei. Together we started working on variation-aware architectures. In detail, we are studying the advantages of using dynamic memories for on-chip structures. Back at UPC, part of this research evolved into the TRAMS and CLERECO projects.

Since 2018, this line of research is focused on system-level analysis and countermeasures within the RECIPE project.

Papers in: Conferences     Journals     Posters

Papers (Conferences)


Posters/Workshops w/o proceedings

Barcelona, July 2020

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