Research activities

Papers

• "Power-Efficient Spilling Techniques for Chip Multiprocessors"
  Enric Herrero, José González, Ramon Canal
  International Conference on Parallel and Distributed Computing, (EURO-PAR'10), Ischia (Italy), September 2010

• "Elastic Cooperative Caching: An Autonomous Dynamically Adaptive Memory Hierarchy for Chip Multiprocessors "
  Enric Herrero, José González, Ramon Canal
  IEEE 37th International Conference on Computer Architecture (ISCA'10), Saint-Malo (France), June 2010

• "Using Coherence Information and Decay Techniques to Optimize L2 Cache Leakage in CMPs"
  Matteo Monchiero, Ramon Canal and  Antonio González
  IEEE 38th International Conference on Parallel Processing (ICPP), Vienna (Austria), September 2009

• "Distributed Cooperative Caching"
  Enric Herrero, José González, Ramon Canal
  IEEE/ACM 17th International Conference on Parallel Architectures and Compilation Techniques (PACT), Toronto (CA), Oct.ober 2008

• " Design Space Exploration for Multicore Architectures: A Power/Performance/Thermal View"
  Matteo Monchiero, Ramon Canal and  Antonio González
  The 20th ACM International Conference on Supercomputing (ICS'06), Cairns (Australia)

• " Value Compresson for Efficient Computation " (slides)

Ramon Canal,  Antonio González and James E. Smith
2005 European Conference on Parallel Computing (Europar'05), Lisboa (Portugal); Lecture Notes in Computer Science v. 3648,  pp. 519-529, August 2005

• " Power- and Performance- Aware Architectures (PhD. dissertation) " (slides)

Ramon Canal (Advisors: Antonio González and James E. Smith)
Department of Computer Architecture (UPC-Barcelona) Barcelona (CAT) , June 2004

• " Software- Controlled Operand Gating " (slides)


Ramon Canal,  Antonio González and James E. Smith
Proc. of the International Symposium on Code Generation and Optimization (CGO-2), Palo Alto (CA-USA), pp. 125-136, March 2004

• "Very Low Power Pipelines using Significance Compression" (slides)


Ramon Canal,  Antonio González and James E. Smith
Proc. of the International Symposium on Microarchitecture (MICRO-33), Monterey (CA-USA), pp. 181-190, Dec. 2000. 

Journals

• "Thread Row Buffers: Improving memory performance isolation and throughput in multiprogrammed environments"
  Enric Herrero, José González, Ramon Canal and Dean Tullsen
  IEEE Transactions on Computers, v 62, n. 9, pp. 1879-1892, Sept. 2013

   

• "Distributed Cooperative Caching: An Energy Efficient Memory Scheme for Chip Multiprocessors"
  Enric Herrero, José González, Ramon Canal
  IEEE Transactions on Parallel and Distributed Systems, v. 23, n. 5, pp. 853-861, May 2012.

• "Power/Performance/Thermal Design Space Exploration for Multicore Architectures"
  Matteo Monchiero, Ramon Canal and  Antonio González
  IEEE Transactions on Parallel and Distributed Systems v. 19 n. 5 pp.666-681, May 2008.

• "Power- and Complexity- Aware Issue Queue Designs"


Jaume Abella, Ramon Canal and Antonio González
IEEE Micro vol. 29 n. 5, pp. 50-59, Sept. 2003.

Posters

• "An application-aware adaptive cache organization for tiled micro architectures "
  Enric Herrero, José González, Ramon Canal
  Intel 2010 European Research and Innovation Conference, Brounschweig (Germany), September 2010

• "A Scalable and Power-Efficient Memory Hierarchy for Multicore Architectures"
  Enric Herrero, José González, Ramon Canal
  Intel 2008 European Research and Innovation Conference, Leixlip (Ireland), September 2008

• "Power/Performance/Thermal trade-offs in microarchitecture"
  David Oro, Ramon Canal, Antonio González and James E. Smith
  Intel Academic Forum 2006 Dublin (Ireland), June 2006

• "Design Space Exploration for MulticoreArchitectures: A Power/Performance/Thermal View"
  Matteo Monchiero, Ramon Canal and Antonio González
  Intel Academic Forum 2006 Dublin (Ireland), June 2006

• " Power- and Complexity- Aware Microarchitectures "
  Jaume Abella, Ramon Canal and Antonio González
  Intel Academic Forum 2004 Barcelona (CAT), June 2004