Design for security

Research activities

Secure systems is the another focus of my research at the moment. Research topics include design for secure microarchitectures and secure communications. Since 2019, part of this research is enclosed in the DRAC project (4M€ effort on open architectures in Catalonia) and contributes to the Red-RISCV Spanish RISC-V network .

Papers

"Privacy preserving Deep Learning framework in Fog computing"
N. Gutierrez, E. Rodriguez, S. Mus, B. Otero and R. Canal
6th International Conference on Machine Learning, Optimization, and Data Science (LOD), Siena, Italy, 2020, LNCS 12565.
" Lightweight Protection of Cryptographic Hardware Accelerators against Differential Fault Analysis"
A. Lasheras, R. Canal, E. Rodríguez, L. Cassano
2020 IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS), Naples, Italy, 2020, pp. 1-6.
"Protecting RSA Hardware Accelerators against Differential Fault Analysis through Residue Checking"
A. Lasheras, R. Canal, E. Rodríguez, L. Cassano
2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), Noordwijk, Netherlands, 2019, pp. 1-6.

Journals

"Securing RSA Hardware Accelerators through Residue Checking"
A. Lasheras, R. Canal, E. Rodríguez, L. Cassano
Journal of Microelectronics Reliability, 2021 (Accepted)

Posters

None at the moment

Barcelona, Dec 2020