Publications
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Conferences
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Petar Radojkovic,
Vladimir Cakarevic, Miquel
Moretó, Javier Verdú,
Alex Pajuelo, Francisco Cazorla,
Mario Nemirovsky, and Mateo Valero
"Optimal Task Assignment in Multithreaded Processors: A
Statistical Approach"
In Procs. of 17th International Conference on
Architectural Support for Programming Languages and Operating Systems
(ASPLOS), London, UK, March 3-7, 2012.
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Ruken Zilan,
Javier Verdú, Jorge García,
Mario Nemirovsky, Rodolfo Milito,
and Mateo Valero
"An Abstraction Methodology for the Evaluation of Multi-core
Multi-threaded Architectures"
In Procs. of 19th Annual Meeting of the IEEE
International Symposium on Modeling, Analysis and
Simulation of Computer and Telecommunication Systems (MASCOTS), Singapore,
July 25-27, 2011.
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Petar Radojkovic,
Vladimir Cakarevic, Javier Verdú,
Alex Pajuelo, Francisco J. Cazorla,
Mario Nemirovsky, and Mateo Valero
"Thread to Strand Binding of Parallel Network Applications in
Massive Multi-Threaded Systems"
In Procs. of 15th ACM SIGPLAN Annual Symposium on
Principles and Practice of Parallel Programming (PPoPP),
Bangalore, India, Janaury 9-14, 2010.
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Vladimir Cakarevic, Petar Radojkovic, Javier Verdú, Alex Pajuelo, Francisco J. Cazorla,
Mario Nemirovsky and Mateo Valero
"Characterizing the resource-sharing levels in the UltraSPARC T2 Processor"
In Procs. of 42nd Annual IEEE/ACM International
Symposium on Microarchitecture (MICRO), New York
City, USA, December 12-16, 2009.
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Ruken Zilan,
Javier Verdú, Jorge García,
Mario Nemirovsky, and Mateo Valero
"Internet Traffic and the Behavior of
Processing Workloads"
In Poster Abstracts Procs. of 5th International
Summer School on Advanced Computer Architecture and Compilation for Embedded
Systems (ACACES), pp. 269-272, Terrasa, Spain, July
12 - 18, 2009.
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Petar Radojkovic,
Vladimir Cakarevic, Javier Verdú,
Alex Pajuelo, Roberto Gioiosa,
Francisco J. Cazorla, Mario Nemirovsky,
and Mateo Valero
"Measuring Operating System Overhead on Sun UltraSPARC
T1 Processor"
In Poster Abstracts Procs. of 5th International
Summer School on Advanced Computer Architecture and Compilation for Embedded
Systems (ACACES), pp. 187-190, Terrasa, Spain, July
12 - 18, 2009.
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Javier Verdú, David López, and Alex Pajuelo
"Mapa Conceptual Global como Herramienta para la Visión Global
de un Sistema Operativo"
In Procs. of 15th Jornadas de Enseñanza
Universitaria de la Informática (JENUI), Granada, Spain,
July 8-10, 2009.
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Javier Verdú, Alex Pajuelo,
and David López
"Experiencias en el uso de un Mapa Conceptual Global en SO"
In Procs. of Jornadas Docentes del Departamento de
Arquitectura de Computadores (JoDoDAC), Barcelona, Spain, February, 2009.
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Javier Verdú and Mario Nemirovsky
"A New Era of Processors for a New Era of Network Services"
Nerd Lunch Seminar, Cisco Systems, San Jose, CA, November, 2008.
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Javier Verdú, Mario Nemirovsky, and
Mateo Valero
"MultiLayer Processing – An Execution
Model for Parallel Stateful Packet Processing"
In Procs. of 4th ACM/IEEE Symposium on
Architecture for Networking and Communications Systems (ANCS-IV), San Jose,
CA, November, 2008.
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Petar Radojkovic,
Vladimir Cakarevic, Javier Verdú,
Alex Pajuelo, Roberto Gioiosa,
Francisco Cazorla, Mario Nemirovsky, and Mateo Valero
"Measuring Operating System Overhead on CMT Processors"
In Procs. of International Symposium on Computer
Architecture and High Performance Computing (SBAC-PAD), Campo
Grande – Mato Grosso
do Sul,
Brazil,
October, 2008.
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Vladimir Cakarevic, Petar Radojkovic, Javier Verdú, Alex Pajuelo, Roberto Gioiosa,
Francisco Cazorla, Mario Nemirovsky, and Mateo Valero
"Understanding the Overhead of the Spin-Lock Loop in CMT
Architectures"
In Procs. of Workshop on the Interaction between
Operating Systems and Computer Architecture (WIOSCA), held in conjunction
with ISCA-35, Beijing, China, June, 2008.
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Javier Verdú, David López, and Alex Pajuelo
"Montando el puzzle: Visión global de un
Sistema Operativo"
In Procs. of Jornadas de Enseñanza Universitaria de
la Informática (JENUI), Granada, Spain, July, 2008.
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Javier Verdú, Alex Pajuelo,
and David López
"Una metodología para obtener la visión global de un SO"
In Procs. of Jornadas Docentes del Departamento de
Arquitectura de Computadores (JoDoDAC), Barcelona, Spain, February, 2008.
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Javier Verdú, Mario Nemirovsky, and Mateo Valero
"Parallelizing Deep Packet Processing in Highly Parallel
Architectures"
In Poster Abstracts Procs. of Advanced Computer
Architecture and Compilation for Embedded Systems (ACACES), pp.71-74.
L’Aquila, July, 2007.
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Javier Verdú, Jorge García, Mario Nemirovsky, and
Mateo Valero
"Architectural Impact of Stateful
Networking Applications"
In Procs. of 1st Symposium on Architecture for
Networking and Communications Systems (ANCS-I). Princeton, NJ, October 2005.
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Javier Verdú, Jorge García, Mario Nemirovsky, and
Mateo Valero
"Analysis of Traffic Traces for Stateful
Applications"
XVI Jornadas de Paralelismo.
Granada, Spain, September
2005.
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Javier Verdú, Mario Nemirovsky, Jorge García,
and Mateo Valero
"Workload Characterization of Stateful
Networking Applications"
In 6th International Symposium on High Performance Computing (ISHPC-VI). Nara, Japan,
September 2005. Also appears as Lecture Notes on Computer Science, .
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Raimir Holanda,
Javier Verdú, Jorge García,
and Mateo Valero
"Performance Analysis of a New Packet Trace Compressor based on
TCP Flow Clustering"
In Procs. of IEEE International Symposium on
Performance Analysis of Systems and Software (ISPASS). Austin, TX, March 2005.
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Javier Verdú, Jorge García, Mario Nemirovsky, and
Mateo Valero
"The Impact of Traffic Aggregation on the Memory Performance of
Networking Applications"
In Workshop on Memory performance: Dealing with Applications, systems, and
architecture (MEDEA), held in conjunction with PACT. Antibes - Juan Les Pins,
France, September 2004.
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Javier Verdú, Jorge García, Mario Nemirovsky, and
Mateo Valero
"Analysis of Traffic Traces for Stateful
Applications"
XV Jornadas de Paralelismo.
Almería, Spain, September
2004.
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Javier Verdú, Jorge García, Mario Nemirovsky, and
Mateo Valero
"Analysis of Traffic Traces for Stateful
Applications"
In Workshop on Network Processors & Applications (NP3), held in
conjunction with HPCA-10. Madrid, Spain, February 2004.
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Javier Verdú, Jesús Corbal,
Jorge García, and Mateo Valero
"Retos en el diseno de Network Processors"
XIII Jornadas de Paralelismo. Lleida, Spain, September 2002.
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Journals
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Javier Verdú, Alex Pajuelo, and Mateo
Valero
"The Problem of Evaluating CPU+GPU Systems with 3D Visualization
Applications"
In IEEE Micro, Volume XX, Issue 99, PrePrint, Feb,
2012. IEEE Computer Society Digital Library. IEEE Computer Society, http://doi.ieeecomputersociety.org/10.1109/MM.2012.13
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Petar Radojkovic,
Vladimir Cakarevic, Javier Verdú,
Alex Pajuelo, Francisco J. Cazorla,
Mario Nemirovsky, and Mateo Valero
"Thread to Strand Binding of Parallel Network Applications in
Massive Multi-Threaded Systems"
In ACM SIGPLAN Notices - PPoPP '10, Volume 45,
Issue 5, pp. 191-202, May, 2010.
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Javier Verdú, Jorge García, Mario Nemirovsky, and Mateo Valero
"The Impact of Traffic Aggregation on the Memory Performance of
Networking Applications"
In Journal of Embedded Computing (JEC) , Volume 2,
Number 1, pp. 77-82, 2006.
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Javier Verdú, Jorge García, Mario Nemirovsky, and Mateo Valero
"The Impact of Traffic Aggregation on the Memory Performance of
Networking Applications"
In ACM SIGARCH Computer Architecture News, Special Issue: MEDEA 2004
Workshop, volume 33, issue 3, pp. 57-62, June, 2005.
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Books
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Alex Pajuelo, David López, Amador Millán,
Ana Heredero, Alex Durán, J.R. Herrero, Javier Verdú,
Yolanda Becerra, Enric Morancho
"Sistemes Operatius.
Quadern de Laboratori (e-book)"
Barcelona, 2007. ISBN: 978-84-612-1022-2.
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Alex Pajuelo, David López, Amador Millán,
Ana Heredero, Alex Durán, J.R. Herrero, Javier Verdú,
Yolanda Becerra, Enric Morancho
"Sistemes Operatius.
Quadern de Laboratori
"
Barcelona, 2007. ISBN: 978-84-612-0288-1.
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Final
Project Informatics Engineering
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Pol Uros (Director: Javier Verdú; Ponente:
Alex Pajuelo)
"Emulación del tiempo en aplicaciones instrumentadas"
Enginyeria Tècnica en Informàtica de Sistemes.
Barcelona, July, 2009.
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Xavier Górriz (Director: Alex Pajuelo; Co-Director: Javier Verdú)
"Análisis del rendimiento de DirectX"
Enginyeria en Informàtica.
Barcelona, July, 2009.
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Jaume Palencia (Director: Javier Verdú;
Ponente: Alex Pajuelo)
"Sistema automático de bots para Quake 3"
Enginyeria en Informàtica.
Barcelona, November, 2008.
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