Joan-Manuel Parcerisa Professor Agregat (now retired) email:   jmanel  AT  ac DOT upc DOT edu Department of Computer Architecture  Universitat Politècnica de Catalunya (UPC) c. Jordi Girona 31, Campus Nord 08034 Barcelona, Spain

List of Publications

• LIBRA: Memory Bandwidth- and Locality-Aware Parallel Tile Rendering
  Aurora Tomás, Juan L. Aragón, Joan-Manuel Parcerisa and Antonio González
  in Proceedings of the 57th IEEE/ACM International Symposium on Microarchitecture (MICRO 2024), November 2 2024, doi: 10.1109/MICRO61859.2024.00081

• Boustrophedonic Frames: Quasi-Optimal L2 Caching for Textures in GPUs
  Diya Joseph, Juan L. Aragón, Joan-Manuel Parcerisa and Antonio González
  in Proceedings of the 32nd International Conference on Parallel Architectures and Compilation Techniques (PACT 2023), October 21-25 2023, doi: 10.1109/PACT58117.2023.00019

• DTexL: Decoupled Raster Pipeline for Texture Locality
  Diya Joseph, Juan L. Aragón, Joan-Manuel Parcerisa and Antonio González
  Proceedings of the 55th IEEE/ACM Int'l Symp. on Microarchitecture (MICRO 2022), October 1-5 2022, doi:10.1109/MICRO56248.2022.00028

• Triangle Dropping: An Occluded-Geometry Predictor for Energy-Efficient Mobile GPUs
  David Corbalán-Navarro, Juan L. Aragón, Martí Anglada, Joan-Manuel Parcerisa and Antonio González
  ACM Transactions on Architecture and Code Optimization (TACO), Vol. 19, No. 3, Article 39, May 2022, doi:10.1145/3527861

• Dynamic Sampling Rate: Harnessing Frame Coherence in Graphics Applications for Energy-Efficient GPUs
  Martí Anglada, Enrique de Lucas, Joan-Manuel Parcerisa, Juan L. Aragón and Antonio González
  The Journal of Supercomputing, September 2022, doi:10.1007/s11227-022-04413-7

• TCOR: A Tile Cache with Optimal Replacement
  Diya Joseph, Juan L. Aragón, Joan-Manuel Parcerisa and Antonio González
  Proceedings of the 2022 IEEE Int'l Symp. on High-Performance Computer Architecture (HPCA-28), April 2-6, 2022, doi: 10.1109/HPCA53966.2022.00055

• DTM-NUCA: Dynamic Texture Mapping-NUCA for Energy-Efficent Graphics Rendering
  David Corbalán-Navarro, Juan L. Aragón, Joan-Manuel Parcerisa and Antonio González
  Proceedings of the 30th. Euromicro Intl' Conf. on Parallel, Distributed and Network-based Processing (PDP 2022), March 9-11, 2022, doi: 10.1109/PDP55904.2022.00030

• Improving the Energy Efficiency of the Graphics Pipeline by Reducing Overshading
  David Corbalán-Navarro, Juan L. Aragón, Martí Anglada, Enrique de Lucas, Joan-Manuel Parcerisa and Antonio González
  Actas de las Jornadas SARTECO 2021, Septiembre 21, 2021

• Omega-Test: A Predictive Early-Z Culling to Improve the Graphics Pipeline Energy-Efficiency
  David Corbalán-Navarro, Juan L. Aragón, Martí Anglada, Enrique de Lucas, Joan-Manuel Parcerisa and Antonio González
  IEEE Transactions on Visualization and Computer Graphics, June 2021, doi: 10.1109/TVCG.2021.3087863.

• Early Visibility Resolution for Removing Ineffectual Computations in the Graphics Pipeline
  Martí Anglada, Enrique de Lucas, Joan-Manuel Parcerisa, Juan L. Aragón, Antonio González
  25th. Int. Symp. on High-Performance Computer Architecture (HPCA 25), pp. 635-646, February 2019, doi: 10.1109/HPCA.2019.00015.

• Rendering Elimination: Early Discard of Redundant Tiles in the Graphics Pipeline
  Martí Anglada, Joan-Manuel Parcerisa, Enrique de Lucas, Juan L. Aragón, Pedro Marcuello, Antonio González
  25th. Int. Symp. on High-Performance Computer Architecture (HPCA 25), pp. 623-634, February 2019, doi: 10.1109/HPCA.2019.00014.

• Visibility Rendering Order: Improving Energy Efficiency on Mobile GPUs through Frame Coherence
  Enrique de Lucas, Pedro Marcuello, Joan-Manuel Parcerisa and Antonio González
  IEEE Transactions on Parallel and Distributed Systems, 30 (2): 473-485. IEEE Computer Society, February 2019, doi: 10.1109/TPDS.2018.2866246

• An Energy-Efficient Memory Unit for Clustered Microarchitectures
  Stefan Bieschewski, Joan-Manuel Parcerisa and Antonio González
  IEEE Transactions on Computers, 65 (8):2631-2637. IEEE Computer Society, August 2016, doi: 10.1109/TC.2015.2493518

• Ultra-low Power Render-Based Collision Detection for CPU/GPU Systems
  Enrique de Lucas, Pedro Marcuello, Joan-Manuel Parcerisa and Antonio González
  48th Int. Symp. on Microarchitecture (MICRO 2015), pp. 445-456, December 2015, doi: 10.1145/2830772.2830783

• Eliminating Redundant Fragment Shader Executions on a Mobile GPU via Hardware Memoization
  José-María Arnau, Joan-Manuel Parcerisa and Polychronis Xekalakis
  41st Int. Symp. on Computer Architecture (ISCA 2014), pp. 529-540, June 2014, doi: 10.1109/ISCA.2014.6853207

• Parallel Frame Rendering: Trading Responsiveness for Energy on a Mobile GPU
  José-María Arnau, Joan-Manuel Parcerisa and Polychronis Xekalakis
  22nd Int. Conf. on Parallel Architectures and Compilation Techniques (PACT 2013), pp. 83-92, September 2013, doi: 10.1109/PACT.2013.6618806.

• TEAPOT: A Toolset for Evaluating Performance, Power and Image Quality on Mobile Graphics Systems
  José-María Arnau, Joan-Manuel Parcerisa and Polychronis Xekalakis
  27th Int. Conf. on Supercomputing (ICS 2013), pp. 37-46, June 2013, doi: 10.1145/2464996.2464999.

• La influencia del orden de las preguntas en los exámenes de primer curso
  David López, Jordi Cortés-Martínez, Montse Fernández, Joan-Manuel Parcerisa, Rubèn Tous and Jordi Tubella
  XIX Jornadas de Enseñanza Universitaria de la Informática (JENUI 2013), pp. 143-150, July 2013

• A Decoupled Access/Execute Architecture for Mobile GPUs
  José-María Arnau, Joan-Manuel Parcerisa and Polychronis Xekalakis
  8th. Int. Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems (ACACES 2012), pp. 17-20, July 2012.

• Boosting Mobile GPU Performance with a Decoupled Access/Execute Fragment Processor
  José-María Arnau, Joan-Manuel Parcerisa and Polychronis Xekalakis
  39th. Int. Symp. on Computer Architecture (ISCA-2012), pp. 84-93, June 2012, doi: 10.1109/ISCA.2012.6237008
  Also published as a journal in ACM SIGARCH Computer Architecture News, 2012, vol. 40, no. 3

• Leveraging Register Windows to Reduce Physical Registers to the Bare Minimum
  Eduardo Quiñones, Joan-Manuel Parcerisa and Antonio González
  IEEE Transactions on Computers, 59 (12):1598-1610. IEEE Computer Society, December 2010

• Work in Progress--Improving Feedback Using an Automatic Assessment Tool
  Daniel Jiménez-González, Carlos Álvarez, David López, Joan-Manuel Parcerisa, Javier Alonso, Christian Pérez, Ruben Tous, Pere Barlet, Montse Fernández, and Jordi Tubella
  38th. Annual ASEE/IEEE Frontiers in Education Conference (FIE'08), pp. S3B-9 -- T1A-10, October 2008, doi: 10.1109/FIE.2008.4720591

• SISA-EMU: Feedback automático para ensamblador
  Carlos Álvarez, Daniel Jiménez-González, David López, Javier Alonso, Ruben Tous, Joan-M. Parcerisa, Pere Barlet, Montse Fernández, Jordi Tubella and Christian Pérez
  XIV Jornadas de Enseñanza Universitaria de la Informática (JENUI 2008), pp. 557-564, July 2008

• Early Register Release for Out-of-Order Processors with Register Windows
  Eduardo Quiñones, Joan-Manuel Parcerisa and Antonio González
  2007 Int. Conf. on Parallel Architectures and Compilation Techniques (PACT-2007), pp. 225-234, September 2007, doi = 10.1109/PACT.2007.4336214

• Improving Branch Prediction and Predicated Execution in Out-of-Order Processors
  Eduardo Quiñones, Joan-Manuel Parcerisa and Antonio González
  13th. Int. Symp. on High-Performance Computer Architecture (HPCA-13), pp. 75-84, February 2007, doi: 10.1109/HPCA.2007.346186

• Selective Predicate Prediction for Out-of-Order Processors
  Eduardo Quiñones, Joan-Manuel Parcerisa and Antonio González
  2006 Int. Conf. on Supercomputing (ICS06), pp. 46-54, June 2006, doi: 10.1145/1183401.1183410

• Memory Bank Predictors
  Stefan Bieschewski, Joan-Manuel Parcerisa and Antonio González
  2005 IEEE Int. Conf. on Computer Design (ICCD-2005), pp. 666-668, October 2005, doi: 10.1109/ICCD.2005.73

• On-Chip Interconnects and Instruction Steering Schemes for Clustered Microarchitectures
  Joan-Manuel Parcerisa, Julio Sahuquillo, Antonio González and José Duato
  IEEE Transactions on Parallel and Distributed Systems, 16(2):130-144, IEEE Computer Society, February 2005.

• Design of Clustered Superscalar Microarchitectures (poster)
  Joan-Manuel Parcerisa and Antonio González
  9th EMEA International Academic Forum, Intel Higher Education Program, April 2004

• Efficient Interconnects for Clustered Microarchitectures
  Joan-Manuel Parcerisa, Julio Sahuquillo, Antonio González and José Duato
  2002 Int. Conf. on Parallel Architectures and Compilation Techniques (PACT-2002), pp. 291-300, September 2002, doi: 10.1109/PACT.2002.110602

• Improving Latency Tolerance of Multithreading through Decoupling
  Joan-Manuel Parcerisa and Antonio González.
  IEEE Transactions on Computers, 50 (10): 1084-1094, IEEE Computer Society, October 2001

• Dynamic Code Partitioning for Clustered Architectures
  Ramon Canal, Joan Manuel Parcerisa and Antonio González
  International Journal of Parallel Programming, 29 (1): 59-79, Kluwer Academic/Plenum Publishers, February 2001

• Reducing Wire Delay Penalty through Value Prediction
  Joan-Manuel Parcerisa and Antonio González
  33rd. Annual IEEE/ACM Int. Symp. on Microarchitecture (MICRO-33), pp. 317-326, December 2000, doi: 10.1145/360128.360163

• Dynamic Cluster Assignment Mechanisms
  Ramon Canal, Joan Manuel Parcerisa and Antonio González
  6th. Int. Symp. on High-Performance Computer Architecture (HPCA-6), pp. 133-142, January 2000, doi: 10.1109/HPCA.2000.824345

• A Cost-Effective Clustered Architecture
  Ramon Canal, Joan Manuel Parcerisa and Antonio González
  1999 Int. Conf. on Parallel Architectures and Compilation Techniques (PACT-99), pp. 160-168, October 1999, doi: 10.1109/PACT.1999.807517

• The Synergy of Multithreading and Access/Execute Decoupling
  Joan-Manuel Parcerisa and Antonio González
  5th. Int. Symp. on High-Performance Computer Architecture (HPCA-5), pp. 59-63, January 1999, doi: 10.1109/HPCA.1999.744329

• The Latency Hiding Effectiveness of Decoupled Access/Execute Processors
  Joan-Manuel Parcerisa and Antonio González
  24th. Euromicro Conference, (EUROMICRO-98), pp 293-300, August 1998, doi: 10.1109/EURMIC.1998.711813

• Eliminating Cache Conflict Misses Through XOR-Based Placement Functions
  Antonio González, Mateo Valero, Nigel Topham and Joan M. Parcerisa
  1997 Int. Conf. on Supercomputing (ICS-97), pp. 76-83, July 1997, doi: 10.1145/263580.263599

My PhD thesis

• Design of Clustered Superscalar Microarchitectures
  Joan-Manuel Parcerisa
  Universitat Politècnica de Catalunya, 17/06/2004
  Also registered as a Technical Report in the Computer Architecture Department repository, as UPC-DAC-2004-49

Research

Past PhD. students:

• Aurora Tomàs
• Diya Joseph
  Improving Memory Access Efficiency for Real-time Rendering in Tile-based GPU Architectures (PhD defense 26/07/2024)
• David Corbalán
  Diseño de GPUs eficientes energéticamente explotando la coherencia entre fotogramas y optimizando los accesos a memoria (PhD defense 26/06/2023)
• Martí Anglada
  Exploiting frame coherence in real-time rendering for energy-efficient GPUs (local-copy) (PhD defense 09/06/2020)
• Enrique De Lucas
  Reducing Redundancy of Real Time Computer Graphics in Mobile Systems (PhD defense 20/04/2018)
• José María Arnau
  Energy-Efficient Mobile GPU Systems (PhD defense 24/04/2015)
• Stefan Bieschewski
  Design of a Distributed Memory Unit for Clustered Microarchitectures (PhD defense 20/06/2013)
• Eduardo Quiñones
  Predicated Execution and Register Windows for Out-of-Order Processors (PhD defense 18/11/2008)

Teaching

• Past teaching in the undergraduate course: Estructura de Computadors
  This course is part of the Grade studies of Computer Science Engineering, in the Facultat d'Informàtica de Barcelona of the UPC (english version)

Short Bio

Joan-Manuel Parcerisa received his M.S. and Ph.D. degrees in Computer Science from the Universitat Politècnica de Catalunya (UPC), in Barcelona, Spain, in 1993 and 2004 respectively. Since 1994 he was a professor at the Computer Architecture Department in the Universitat Politècnica de Catalunya until 2024, when he retired. His main research focused on power-efficient GPU architectures for mobile devices. Other research topics included decoupled access/execute architectures, clustered microarchitectures, predication for O-o-O execution and cache memories.