|
|
Academic Information
I obtained the electronic engineering degree
from the University of Antioquia, in
Medellín, Colombia, in 2000. Once I become graduated, I started my first Job
in a Telecommunication Company in Medellín. One year later, I decided to go
back to University and I worked as an Assistant Teacher and Assistant
Researcher in the same University with the Microelectronics Group. In 2002, I
joined the High Performance Computing Group from Department of Computer Architecture in the Universitat Politècnica de Catalunya (Barcelona, Spain).
Since 2006-09-12 I am working as a
Collaborator Professor at the FIB
(UPC). I am teaching the course “Introducción
a los Computadores”. That is, the basics of Computer systems (logic
circuits). Even though teaching is a very time consuming activity, I really
enjoy doing this!! ;-), I think I learn too much when I teaching.
Part of my research in my PhD studies have been focused on computer
architecture for multimedia processing. This work has been made under
supervision of Doctor Alex Ramirez and Doctor Mateo Valero.
My PhD thesis focuses on processor microarchitectures for biology
applications, specifically on biological sequence comparison applications,
like Smith Waterman algorithm, Blast and Fasta Applications. Currently, I am
working on Processor architectures for multimedia and bioinformatic
applications; Analysis and evaluation of current SIMD extensions and Analysis
and evaluation of Smith-Waterman, Blast and FASTA algorithms for biological
sequence Comparison.
Also, I am interested in application specific processors for multimedia
applications in embedded systems, vector processors and SIMD extensions,
performance evaluation and workload characterization, simulation methodologies
for processor microarchitecture.
Research Experience
·
Fellowship Holder, High Performance Computing Group in the Computer
Architecture Department, Universitat Politècnica de Catalunya (DAC-UPC),
Advisors: Mateo Valero and Alex Ramirez.
·
Research Assistant in the Microelectronic Laboratory. Universidad
de Antioquia, Medellín, Colombia Jun.1998 - Dec 2001. Implementing DSP architectures in FPGAs using
distributed arithmetic. Design of embedded architectures for fuzzy systems
using FPGAs. Supervisor: Professor José Edinson Aedo.
·
Assistant Teacher of Digital circuit design course. Universidad
de Antioquia. Medellín, Colombia 1999-2000. Professor Eugenio Duque Pérez
·
Teacher of the laboratory of Digital Circuits design and VHDL
programming. Supervisor: Professor Eugenio Duque Pérez. Universidad de
Antioquia. Medellín, Colombia 2001.
Technical Publications
 Friman. Sánchez,
Esther. Salami, Alex. Ramirez and Mateo. Valero: “Performance
Analysis of Sequence Alignment Applications”. IEEE International Symposium on
Workload Characterization IISWC, San
José, California, USA, October 2006. (Download paper)
Friman. Sánchez,
Esther. Salami, Alex. Ramirez and Mateo. Valero: “Parallel
processing in biological sequences comparison using general purpose
processors”. IEEE
International Symposium on Workload Characterization IISWC, Austin, USA,
October 2005. (Download paper)
Friman Sánchez, Mauricio Alvarez,
Esther Salamí, Alex Ramirez, Mateo Valero, On the Scalability
of 1- and 2-Dimensional SIMD Extensions for Multimedia Applications, 2005 IEEE International Symposium
on Performance Analysis of Systems and Software. Austin, USA.
March 2005. (Download paper)
Mauricio Alvarez, Friman Sánchez, Esther Salamí, Alex Ramirez, Mateo
Valero, “Scalability and Complexity of 2-Dimensional SIMD
Extensions”. XVI Jornadas de Paralelismo. Computación de
altas prestaciones. Spain, September 2004. (Download paper)
Friman Sanchez, Esther
Salami, Alex Ramirez and Mateo Valero. “Parallel Processing in
Sequence Matching”, Poster presentation in ACACES 2005, Advanced
Computer Architecture and Compilation for embedded Systems.”
L`Aquila, Italy,
July 2005. (Download
poster)
F. Sánchez and J.E Aedo, “Design
of high complexity fuzzy controllers using generic VHDL for appliance
applications”. VIII International Workshop Iberchip IWS2002. Guadalajara, Mexico, April 2002. (Download paper)
F. Sánchez and J. F. Osorio.
“Design and implementation of a Digital Signal
Processing ASIC”. Technical Report
presented to obtain the Electronic Engineering Degree. Universidad de Antioquia 2000. (Download report) (In spanish)
|
|
